Understanding RAM Timing Is Crucial To Overclocking A Computer

When buying RAM, buying the fastest RAM with the lowest RAM timing will help you get the most out of your computer.  If you're serious about building a really fast computer, or have even considered overclocking, paying attention to RAM timing along with everything else will get you the best computer you can make.

Advanced Timing Information

There are many different timings that effect the speed RAM runs at, MHz is one, but often, you will see another set of numbers, like 5-6-8-15 for example, this refers to the RAM timing.  The first number refers to CAS Latency, or CL, the 2nd number to RAS to CAS delay or tRCD, the 3rd number refers to RAS precharge or tRP, and finally the last number refers to Cycle Time or tRAS.

If you would like to see the current timing of your RAM, you can use a little program called CPU-Z to find out what your timing needs to be set at.  This little tool is must when overclocking the FSB, it will help you keep your RAM speed in check.

What Does All This Timing Mean

All the information below in Italics is courtesy of Wikepedia, unless otherwise noted.

Column Address Strobe (CAS) latency, or CL, is the delay time between the moment a memory controller tells the memory module to access a particular memory column on a RAM memory module, and the moment the data from given array location is available on the module's output pins. In general, the lower the CAS latency, the better.

tRCD (RAS to CAS Delay) is the number of clock cycles needed between a row address strobe (RAS) and a CAS. It is the time required between the computer defining the row and column of the given memory block and the actual read or write to that location. tRCD stands for row address to column address delay.

tRP (RAS Precharge) is the number of clock cycles needed to terminate access to an open row of memory, and open access to the next row. Stands for Row precharge time.

tRAS (Row Active Time) is the minimum number of clock cycles needed to access a certain row of data in RAM between the data request and the precharge command. It's known as active to precharge delay. According to Mushkin, in practice for DDR SDRAM, this should be set to at least tRCD + tCAS + 2 to allow enough time for data to be streamed out.

tRC (Row Cycle Time) is generally = tRAS + tRP.

Command Rate is the time needed between the chip select signal and when commands can be issued to the RAM module IC. Typically, these are either 1 clock or 2.   (this paragraph courtesty of AMD.com)

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